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1. general description the 74hc7403-q100; 74hct7403-q100 is an expandable, first-in first-out (fifo) memory organized as 64 words by 4 bits. a guaranteed 15 mhz data-rate makes it ideal for high-speed applications. a higher data-rate can be obtained in applications where the status flags are not used (burst-mode). with separate controls for shift-in (si) and shift-out (so ), reading and writing operations are completely independent, allowing synchronous and asynchronous data transfers. additional controls include a master-reset input (mr ), an output enable input (oe ) and flags. the data-in-ready (dir) and data-out-ready (dor) flags indicate the status of th e device. inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? synchronous or asynchronous operation ? 30 mhz (typical) shift- in and shift-out rates ? readily expandable in word and bit dimensions ? pinning arranged for easy board layout: in put pins directly opposite output pins ? input levels: ? for 74hc7403-q100: cmos level ? for 74hct7403-q100: ttl level ? 3-state outputs ? complies with jedec standard jesd7a ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. applications ? high-speed disc or tape controller ? communications buffer 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state rev. 1 ? 21 september 2012 product data sheet
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 2 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 4. ordering information 5. functional diagram table 1. ordering information type number package temperature range name description version 74HC7403D-Q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74hct7403d-q100 fig 1. logic symbol fig 2. iec logic symbol

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74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 4 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 6. pinning information 6.1 pinning 6.2 pin description 7. functional description a dir flag indicates the input stage status, ei ther empty and ready to receive data (dir = high) or full and busy (dir = low). when dir and si are high, data present at d0 to d3 is shifted into the input stage; once co mplete dir goes low. when si is set low, data is automatically shifted to the output stage or to th e last empty location. dir set high indicates a fifo which can receive data. fig 5. pin configuration 1

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table 2. pin description symbol pin description oe 1 output enable input (active low) dir 2 data-in-ready output si 3 shift-in input (active high) d0 to d3 4, 5, 6, 7 parallel data input gnd 8 ground (0 v) mr 9 asynchronous master-rese t input (active low) q0 to q3 13, 12, 11, 10 data output dor 14 data-out-ready output so 15 shift-out input (active low) v cc 16 supply voltage
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 5 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state a dor flag indicates the output stage status, either data available (dor = high) or busy (dor = low). when so and dor are high, data is avail able at the outputs (q0 to q3). when so is set low new data may be shifted into the output stage, once complete dor is set high. 7.1 expanded format the dor and dir signals are used to allow the 74hc7403-q100; 74hct7403-q100 to be cascaded. both parallel and serial expansion is possible. (see figure 18 ). serial expansion is only possible with typical devices. 7.1.1 parallel expension parallel expension is accomplished by logically anding the dor and dir signals to form a composite signal. 7.1.2 serial expension parallel expension is accomplished by: ? tying the data outputs of the first device to the data inputs of the second device. ? connecting the dor pin of the first devic e to the si pin of the second device. ? connecting the so pin of the first device to th e dir pin of the second device. 8. limiting values [1] for so16 packages: above 70 ? c the value of p tot derates linearly with 8 mw/k. table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7 v i ik input clamping current v i < ? 0.5 v or v i >v cc +0.5 v - ? 20 ma i ok output clamping current v o < ? 0.5 v or v o >v cc +0.5v - ? 20 ma i o output current v o = ? 0.5 v to (v cc +0.5v) - ? 35 ma i cc supply current - +70 ma i gnd ground current - ? 70 ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation [1] - 500 mw
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 6 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 9. recommended operating conditions 10. static characteristics table 4. recommended operating conditions voltages are referenced to gnd (ground = 0 v) symbol parameter conditions 74hc7403-q100 74hct7403-q100 unit min typ max min typ max v cc supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 v v i input voltage 0 - v cc 0- v cc v v o output voltage 0 - v cc 0- v cc v t amb ambient temperature ? 40 +25 +125 ? 40 +25 +125 ?c ? t/ ? v input transition rise and fall rate v cc = 2.0 v - - 625 - - - ns/v v cc = 4.5 v - 1.67 139 - 1.67 139 ns/v v cc = 6.0 v--83---ns/v table 5. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max 74hc7403-q100 v ih high-level input voltage v cc = 2.0 v 1.5 1.2 - 1.5 - 1.5 - v v cc = 4.5 v 3.15 2.4 - 3.15 - 3.15 - v v cc = 6.0 v 4.2 3.2 - 4.2 - 4.2 - v v il low-level input voltage v cc = 2.0 v - 0.8 0.5 - 0.5 - 0.5 v v cc = 4.5 v - 2.1 1.35 - 1.35 - 1.35 v v cc = 6.0 v - 2.8 1.8 - 1.8 - 1.8 v v oh high-level output voltage v i =v ih or v il i o = ? 20 ? a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - v i o = ? 20 ? a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - v i o = ? 20 ? a; v cc = 6.0 v 5.9 6.0 - 5.9 - 5.9 - v i o = ? 8ma; v cc = 4.5 v 3.98 4.32 - 3.84 - 3.7 - v i o = ? 10 ma; v cc = 6.0 v 5.48 5.81 - 5.34 - 5.2 - v v ol low-level output voltage v i =v ih or v il i o =20 ? a; v cc = 2.0 v - 0 0.1 - 0.1 - 0.1 v i o =20 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o =20 ? a; v cc = 6.0 v - 0 0.1 - 0.1 - 0.1 v i o = 8 ma; v cc = 4.5 v - 0.15 0.26 - 0.33 - 0.4 v i o =10ma; v cc = 6.0 v - 0.15 0.26 - 0.33 - 0.4 v i i input leakage current v i =v cc or gnd; v cc =6.0v -- ? 0.1 - ? 1.0 - ? 1.0 ? a i oz off-state output current v i =v ih or v il ; v o =v cc or gnd; v cc =6.0v -- ? 0.5 - ? 5.0 - ? 10.0 ? a
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 7 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state i cc supply current v i =v cc or gnd; i o =0a; v cc =6.0v - - 50 - 500 - 1000 ? a c i input capacitance -3.5- pf 74hct7403-q100 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 1.6 - 2.0 - 2.0 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - 1.2 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il ; v cc =4.5v i o = ? 20 ? a 4.4 4.5 - 4.4 - 4.4 - v i o = ? 8 ma 3.98 4.32 - 3.84 - 3.7 - v v ol low-level output voltage v i =v ih or v il ; v cc =4.5v i o =20 ? a - 0 0.1 - 0.1 - 0.1 v i o = 8 ma - 0.15 0.26 - 0.33 - 0.4 v i i input leakage current v i =v cc or gnd; v cc =5.5v -- ? 0.1 - ? 1.0 - ? 1.0 ? a i oz off-state output current v i =v ih or v il ; v cc =5.5v; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0a -- ? 0.5 - ? 5.0 - ? 10 ? a i cc supply current v i =v cc or gnd; i o =0a; v cc =5.5v - - 50 - 500 - 1000 ? a ? i cc additional supply current v i =v cc ? 2.1 v; other inputs at v cc or gnd; v cc = 4.5 v to 5.5 v; i o =0a per input pin; dn inputs - 75 270 - 338 - 368 ? a per input pin; oe input - 100 360 - 450 - 490 ? a per input pin; si input - 150 540 - 675 - 735 ? a per input pin; mr input - 150 540 - 675 - 735 ? a per input pin; so input - 150 540 - 675 - 735 ? a c i input capacitance -3.5- pf table 5. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 8 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 11. dynamic characteristics table 6. dynamic characteristics voltages are referenced to gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit see figure 17 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ? c unit min typ max min max min max 74hc7403-q100 t pd propagation delay mr to dir or dor; see figure 8 [1] v cc = 2.0 v - 69 210 - 265 - 315 ns v cc = 4.5 v - 25 42 - 53 - 63 ns v cc = 6.0 v - 20 36 - 45 - 54 ns si to dir; see figure 6 [1] v cc = 2.0 v - 66 205 - 255 - 310 ns v cc = 4.5 v - 24 41 - 51 - 62 ns v cc =5v; c l =15pf - 15 - - - - - ns v cc = 6.0 v - 19 35 - 43 - 53 ns so to dor; see figure 9 [1] v cc = 2.0 v - 94 290 - 365 - 435 ns v cc = 4.5 v - 34 58 - 73 - 87 ns v cc =5v; c l =15pf - 15 - - - - - ns v cc = 6.0 v - 27 49 - 62 - 74 ns dor to qn; see figure 10 [1] v cc = 2.0 v - 11 35 - 45 - 55 ns v cc = 4.5 v - 4 7 - 9 - 11 ns v cc = 6.0 v - 3 6 - 8 - 9 ns so to qn; see figure 14 [1] v cc = 2.0 v - 105 325 - 406 - 488 ns v cc = 4.5 v - 38 65 - 81 - 98 ns v cc = 6.0 v - 30 55 - 69 - 83 ns t phl high to low propagation delay mr to qn; see figure 8 v cc = 2.0 v - 52 160 - 200 - 240 ns v cc = 4.5 v - 19 32 - 40 - 48 ns v cc = 6.0 v - 15 27 - 34 - 41 ns t plh low to high propagation delay si to dor; see figure 10 [5] v cc = 2.0 v - 2.2 7 - 8.8 - 10.5 ns v cc = 4.5 v - 0.8 1.4 - 1.8 - 2.1 ns v cc = 6.0 v - 0.6 1.2 - 1.5 - 1.8 ns so to dir; see figure 7 [6] v cc = 2.0 v - 2.8 9 - 11.2 - 13.5 ns v cc = 4.5 v - 1.0 1.8 - 2.2 - 2.7 ns v cc = 6.0 v - 0.8 1.5 - 1.9 - 2.3 ns
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 9 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state t en enable time oe to qn; see figure 16 [2] v cc = 2.0 v - 44 150 - 190 - 225 ns v cc = 4.5 v - 16 30 - 38 - 45 ns v cc = 6.0 v - 13 26 - 32 - 38 ns t dis disable time oe to qn; see figure 16 [3] v cc = 2.0 v - 50 150 - 190 - 225 ns v cc = 4.5 v - 18 30 - 38 - 45 ns v cc = 6.0 v - 14 26 - 33 - 38 ns t t transition time qn; see figure 14 [4] v cc = 2.0 v - 14 60 - 75 - 90 ns v cc = 4.5 v - 5 12 - 15 - 18 ns v cc = 6.0 v - 4 10 - 13 - 15 ns t w pulse width si high or low; see figure 6 v cc = 2.0 v 35 11 - 45 - 55 - ns v cc = 4.5 v 7 4 - 9 - 11 - ns v cc = 6.0 v 6 3 - 8 - 9 - ns so high or low; see figure 9 v cc = 2.0 v 70 22 - 90 - 105 - ns v cc = 4.5 v 14 8 - 18 - 21 - ns v cc = 6.0 v 12 6 - 15 - 18 - ns dir high; see figure 7 v cc = 2.0 v 10 41 130 8 165 8 195 ns v cc = 4.5 v 5 15 26 4 33 4 39 ns v cc = 6.0 v 4 12 22 3 28 3 23 ns dor high; see figure 10 v cc = 2.0 v 14 52 160 12 200 12 240 ns v cc = 4.5 v 7 19 32 6 40 6 48 ns v cc = 6.0 v 6 15 27 5 34 5 41 ns mr low; see figure 8 v cc = 2.0 v 120 39 - 150 - 180 - ns v cc = 4.5 v 24 14 - 30 - 36 - ns v cc = 6.0 v 20 11 - 26 - 31 - ns t rec recovery time mr to si; see figure 15 v cc = 2.0 v 80 24 - 100 - 120 - ns v cc = 4.5 v 16 8 - 20 - 24 - ns v cc = 6.0 v 14 7 - 17 - 20 - ns table 6. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit see figure 17 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ? c unit min typ max min max min max
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 10 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state t su set-up time dn to si; see figure 13 v cc = 2.0 v ? 8 ? 36 - ? 6- ? 6-ns v cc = 4.5 v ? 4 ? 13 - ? 3- ? 3-ns v cc = 6.0 v ? 3 ? 10 - ? 3- ? 3-ns t h hold time dn to si; see figure 13 v cc = 2.0 v 135 44 - 170 - 205 - ns v cc = 4.5 v 27 16 - 34 - 12 - ns v cc = 6.0 v 5 13 - 29 - 14 - ns f max maximum frequency si, so burst mode; see figure 11 and figure 12 v cc = 2.0 v 3.6 9.9 - 2.8 - 2.4 - mhz v cc = 4.5 v 18 30 - 14 - 12 - mhz v cc =5v; c l =15pf - 30 - - - - - mhz v cc = 6.0 v 21 36 - 16 - 14 - mhz si, so using flags; see figure 6 and figure 9 v cc = 2.0 v 3.6 9.9 - 2.8 - 2.4 - mhz v cc = 4.5 v 18 30 - 14 - 12 - mhz v cc =5v; c l =15pf - 30 - - - - - mhz v cc = 6.0 v 21 36 - 16 - 14 - mhz si, so cascaded; see figure 6 and figure 9 v cc = 2.0 v - 7.6 - - - - - mhz v cc = 4.5 v - 23 - - - - - mhz v cc = 6.0 v - 27 - - - - - mhz c pd power dissipation capacitance v i =gndtov cc [7] - 475 - - - - - pf table 6. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit see figure 17 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ? c unit min typ max min max min max
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 11 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 74hct7403-q100 t pd propagation delay mr to dir or dor; see figure 8 [1] v cc = 4.5 v - 30 51 - 53 - 63 ns si to dir; see figure 6 [1] v cc = 4.5 v - 25 43 - 54 - 65 ns v cc =5v; c l =15pf - 17 - - - - - ns so to dor; see figure 9 [1] v cc = 4.5 v - 36 61 - 76 - 92 ns v cc =5v; c l =15pf - 17 - - - - - ns dor to qn; see figure 10 [1] v cc = 4.5 v - 7 12 - 15 - 18 ns so to qn; see figure 14 [1] v cc = 4.5 v - 42 72 - 90 - 108 ns t phl high to low propagation delay mr to qn; see figure 8 v cc = 4.5 v - 22 38 - 48 - 57 ns t plh low to high propagation delay si to dor; see figure 10 [5] v cc = 4.5 v - 0.8 1.4 - 1.75 - 2.1 ns so to dir; see figure 7 [6] v cc = 4.5 v - 1.0 1.8 - 2.25 - 2.7 ns t en enable time oe to qn; see figure 16 [2] v cc = 4.5 v - 16 30 - 38 - 45 ns t dis disable time oe to qn; see figure 16 [3] v cc = 4.5 v - 19 30 - 38 - 45 ns t t transition time qn; see figure 14 [4] v cc = 4.5 v - 5 12 - 15 - 18 ns t w pulse width si high or low; see figure 6 v cc = 4.5 v 9 5 - 6 - 8 - ns so high or low; see figure 9 v cc = 4.5 v 14 8 - 18 - 21 - ns dir high; see figure 7 v cc = 4.5 v 5 17 29 4 36 4 44 ns dor high; see figure 10 v cc = 4.5 v 7 21 36 6 45 6 54 ns mr low; see figure 8 v cc = 4.5 v 26 15 - 33 - 39 - ns table 6. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit see figure 17 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ? c unit min typ max min max min max
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 12 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state [1] t pd is the same as t plh and t phl . [2] t en is the same as t pzh and t pzl . [3] t dis is the same as t plz and t phz . [4] t t is the same as t thl and t tlh . [5] this is the ripple through delay. [6] this is the bubble-up delay. [7] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of outputs. t rec recovery time mr to si; see figure 15 v cc = 4.5 v 18 10 - 23 - 27 - ns t su set-up time dn to si; see figure 13 v cc = 4.5 v ? 5 ? 16 - ? 4- ? 4-ns t h hold time dn to si; see figure 13 v cc = 4.5 v 30 18 - 38 - 45 - ns f max maximum frequency si, so burst mode; see figure 11 and figure 12 v cc = 4.5 v 18 30 - 14 - 12 - mhz v cc =5v; c l =15pf - 30 - - - - - mhz si, so using flags; see figure 6 and figure 9 v cc = 4.5 v 18 30 - 14 - 12 - mhz v cc =5v; c l =15pf - 30 - - - - - mhz si, so cascaded; see figure 6 and figure 9 v cc = 4.5 v - 23 - - - - - mhz c pd power dissipation capacitance v i =gndtov cc ? 1.5 v [7] - 490 - - - - - pf table 6. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); c l = 50 pf unless otherwise specified; for test circuit see figure 17 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ? c unit min typ max min max min max
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 13 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 12. waveforms measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. shifting in sequence fifo empty to fifo full (1) dir initially high; fifo is prepared for valid data (2) si set high; data loaded into input stage (3) dir goes low; input stage ?busy? (4) si set low; data from first location ?ripple through? (5) dir goes high; status flag indica tes fifo prepared for additional data (6) repeat process to load 2 nd word through to 64 th word into fifo; dir remains low; with attempt to shift into full fifo, no data transfer occurs. fig 6. propagation delay si input to dir output, the si pulse width and the si maximum frequency 234" -*5+67 $75+67
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74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 14 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. with fifo full; si held high in anticipation of empty location (1) fifo is initially full, shift-in is held high (2) so pulse; data in output stage is unloaded, ? bubble-up? process of empty location begins (3) dir high; when empty location reaches input stage, flag indicates that fifo is prepared for data input (4) dir returns to low; data returns to low; data shift- in to empty location is complete, fifo is full again (5) si set low; necessary to complete shift-in process, dir remains low, because fifo is full fig 7. bubble-up delay so input to dir output and the dir pulse width. %& &% & 9:99;</:, 7<;4= %& 1 1 1 * > * %()
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 15 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. master reset applied with fifo full (1) dir low; output ready high; assume that fifo is full (2) mr pulse low; clears fifo (3) dir goes high; flag indicates input prepared for valid data (4) dor goes low; flag indicates fifo empty (5) qn outputs go low (only last bit is reset) fig 8. propagation delay mr input to dir output, dor output and qn outputs and the mr pulse width. &% & % & $ &%& &% & 1 1 1 * > * %() * %)( * %)(
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 16 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. (1) dor high; no data transfer in progress, valid data is present at the output stage (2) so set high; result in dor going low (3) dor goes low; output stage ?busy? (4) so set low; data in the input stage is unloaded, and new data r eplaces it as empty location ?bubbles-up? to input stage (5) dor goes high; transfer process completed, valid dat a present at output after the specified propagation delay (6) repeat process to unload the 3 rd through the 64 th word from fifo (7) dor remains low; fifo is empty fig 9. propagation delay so input to dor output, the so pulse width and the so maximum frequency. %& $ &%& &% & -*,:;-< $7,:;-<
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*85+67 1 1 1 * %)( * %() 2 34" * >

74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 17 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. with fifo empty; so is held high in anticipation (1) fifo is initially empty. so is held high. (2) si pulse; loads data into fifo and initiates ripple through process (3) dor flag signals the arrival of valid data at the output stage (4) output transition; data arrives at output stage after the s pecified propagation delay between the rising and falling edge of the dor pulse to the qn output (5) dor goes low; data shift-out is completed, fifo is empty again (6) so set low; necessary to complete shift-out proc ess. dor remains low, because fifo is empty fig 10. ripple through delay si input to dor output, propagation delay dor input to qn outputs and the dor pulse width %& $ &%& &% & 6.,,;<*86+:?8 7<;4=
%& 1 1 1 * > * %() * %)( * %() measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. shift-in operation; high speed burst mode in the high-speed mode, the burst-in rate is determined by the minimum shift-in high and shift- in low specifications. the dir status flag is a ?don?t care? condition, and a shift-in pulse c an be applied regardless of the fl ag. an si pulse which would overflow the storage capacity of the fifo is ignored. fig 11. shift-in (si) pulse wid th and maximum frequency (si) %& $ %& &% & 1 * > 2 34"
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 18 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. shift-out operation; high speed burst mode in the high-speed mode, the burst-out rate is determined by the minimum shift-out high and shif t-out low specifications. the dor flag is a ?don?t care? condition, and an so pulse can be applied without regard to the flag. fig 12. shift-in (so ) pulse width and maximum frequency (so ) %& $ &%& &% & 1 * > 2 34" measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. the shaded areas indicate when the output is per mitted to change for predictable output performance fig 13. set-up and hold times %& $ %& * 8 * -: * 8 * -: 1 1 measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. fig 14. propagation delay shift-out input (so ) to data outputs (qn) an d output transition time %& $ &%& 1 1 * %() * () @ @ @ @ * )( * %)(
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 19 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state measurement points are given in table 7 . v ol and v oh are typical voltage output levels that occur with the output load. fig 15. master-reset (mr ) to shift-in (si) recovery time %& % & 1 1 * 6 74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 20 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state test data is given in table 8 . definitions test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. r l = load resistance. s1 = test selection switch. fig 17. test circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aad983 dut v cc v cc v i v o r t r l s1 c l open g table 8. test data type input load s1 position v i t r , t f c l r l t phl , t plh t pzh , t phz t pzl , t plz 74hc7403-q100 v cc 6ns 15pf, 50 pf 1k ? open gnd v cc 74hct7403-q100 3 v 6 ns 15 pf, 50 pf 1 k ? open gnd v cc
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 21 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 13. application information fig 18. expanded fifo (parallel and serial) for in creased word length; 8 bits wide x 64 n-bits 0/9 .* 74 *4 0/9 .* 74* 4 the 74hc7403-q100; 74hct7403-q100 is easily expanded to increase word length. composite dir and dir flags are formed with the addition of an and gate. the basic operation and timing ar e identical to a single fifo, with the exception of an added gate delay on the flags. fig 19. expanded fifo for increased word length; 64 words x 10 bits $ $ $ $ # # %& % !(# ##& %& % !(# # # %& ##& %&
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 22 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state this circuit is only required if the si in put is constantly held high, when the fifo is empty and the automatic shift-in cycles are started or if the so output is constantly held high, when the fifo is fu ll and the automatic shift-out cycles are started (see figure 7 and figure 10 ). fig 20. expanded fifo for increased word length $ $ $ $ a+3, +-.*< a+3 ,+-.*< % % % %
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 23 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 13.1 expanded format figure 21 shows two cascaded fifos providing a capacity of 128 words x 4 bits. figure 22 shows the signals on the nodes of both fifos after the application of the si pulse, when both fifos are initially empty. af ter a ripple through delay, data arrives at the output of fifoa. due to so a being high, a dora pulse is generated. the requirements od sib and dnb are satisfied by the dora pu lse width and the timing between the rising edge of dora and qna. after a second ripple through delay data arrives at the output of fifob. figure 23 shows the signals on the nodes of both fifos after the application of the so b pulse, when both fifos are in itially full. after a bubble- up delay, a dirb pulse is generated, which acts as a so a pulse for fifoa. one word is transferred from the output of fifoa to the input of fifob. the requirements of the so a pulse for fifoa is satisfied by the pulse width of dorb. after a second bubble-up delay an empty space arrives at dna, at which time dira goes high. figure 24 shows the waveforms at all external nodes of both fifos during a complete shift-in and shift-out sequence. the 74hc7403-q100; 74hct7403-q100 is easily cascaded to increase word capacity without exter nal circuitry. in cascaded format, all necessary communica tions are handled by the fifos. figure 22 and figure 23 demonstrate the communication timing between fifoa and fifob. figure 24 provides an overview of pulses and timing of two cascaded fifos, when shifted full and shifted empty again. fig 21. cascading for increased word capacity; 128 words x 4 bits # # $# # # %& # # $# ! !# ' ' $' ' ' $' ! !' ##& %&
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 24 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state (1) fifoa and fifob are initially empty, so a held high in anticipation of data (2) load one word into fifoa; si pulse; applied. results in dir pulse (3) data-out a/ data-in b transition; valid data arrives at fifoa output stage after a specified delay of the dor flag, meeting data input set-up requirements of fifob. (4) dora and sib pulse high; (ripple through delay after sia low) data is unloaded from fifoa as a result of the data output ready pulse, data is shifted into fifob (5) dirb and so a go low; flag indicates that input stage of fi fob is busy, shift-out of fifoa is complete (6) dirb and so a go high automatically; the input stage of fifob is again able to receive data, so is held high in anticipation of additional data (7) dorb goes high; (ripple through delay after sib low) valid dat a is present one propagation delay later at the fifob output stage fig 22. fifo to fifo communication; input timing under empty condition
6.,,;<*86+:?8 7<;4= 6.,,;<*86+:?8 7<;4= 1 1 1 1 1 # # # ' $ #$' ' $ ' ' #
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 25 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state (1) fifoa and fifob initially full, sib held high in anticipati on of shifting in new data as an empty location bubbles-up (2) unload one word from fifob; so pulse applied, results in dor pulse (3) dirb and so a pulse high; (bubble-up delay after so b low) data is loaded into fifob as a result of the dir pulse, data is shifted out of fifoa (4) dora and sib go low; flag indicates that the output stage of fifoa is busy, shift-in of fifob is complete (5) dora and sib go high; flag indicates that valid data is again av ailable at fifoa output stage, sib is held high, awaiting bubble-up of empty location. (6) dira goes high; (bubble-up delay after so a low) an empty location is present at input stage of fifoa fig 23. fifo to fifo communication; output timing under full condition
9:99;</:, 7<;4= 9:99;</:, 7<;4= 1 1 1 1 1 ' ' ' # $ #$' # # '
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 26 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 13.1.1 sequence 1 (both fifos empty, starting shift-in process) after an m r pulse has been applied, fifoa and fifob are empty. the dor flags of fifoa and fifob go low due to no valid da ta being present at the outputs. the dir flags are set high due to the fifos being ready to accept data. so b is held high and two sia pulses are applied (1). these pulses allow two data words to ripple through the output stage of fifoa and the in put stage of fifib (2). when da ta arrives at the output of fifob, a dorb pulse is generated (3). when so b goes low, the first bit is shifted out and a second bit ripples through to the output after which dorb goes high (4). 13.1.2 sequence 2 (fifob runs full) after the mr pulse, a series of 64 si pulses are applied. when 64 words are shifted in, dirb remains low due to fi fob being full (5). dora goes low due to fifoa being empty. see also section 13.1.1 fig 24. waveforms showing the functionality and intercommunication between two fifos (refer to figure 19 ) ' &%& ' &%& # &%& # &%& $ '&%& $ #&%& # %& $ # %& % & ' %& -
0
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 27 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 13.1.3 sequence 3 (fifoa runs full) when 65 words are shifted in, dora remains high due to valid da ta remaining at the output of fifoa. qna remains hi gh, being the polarity of the 65 th word (6). after the 128 th si pulse, dir remains low and both fifos are full (7). additional pulses have no effect. 13.1.4 sequence 4 (both fifos full, starting shift-out) sia is held high and two so b pulses are applied (8). these pulses shift out two words and thus allow two empty locations to bubble-up to the input stage of fifob, and proceed to fifoa (9). when the first em pty location arrives at the input of fifoa, a dira pulse is generated (10) and a new word is shifted into fifoa. sia is made low and now the second empty location reaches the input stage of fifoa, after which dira remains high (11). 13.1.5 sequence 5 (fifoa runs empty) at the start of sequence 5, fifoa contains 63 valid words due to two words being shifted out and one word being shifted in, in sequence 4. and additional series of so b pulses are applied. after 63 so b pulses, all words from fifoa are shifted in fifob. dora remains low (12). 13.1.6 sequence 6 (fifob runs empty) after the next so b pulse, dirb remains high due to the input stage of fifob being empty. after another 63 so b pulses, dorb remains low due to both fifos being empty (14). additional so b pulses have no effect. the last word remains available at the output qn.
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 28 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 14. package outline fig 25. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 29 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 15. abbreviations 16. revision history table 9. abbreviations acronym description cmos complementary metal oxide semiconductor esd electrostatic discharge hbm human body model mm machine model ttl transistor-transistor logic fifo first in first out mil military table 10. revision history document id release date data sheet status change notice supersedes 74hc_hct7403_q100 v.1 20120921 product data sheet - -
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 30 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74hc_hct7403_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved . product data sheet rev. 1 ? 21 september 2012 31 of 32 nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74hc7403-q100; 74hct7403-q100 4-bit x 64-word fifo register; 3-state ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 21 september 2012 document identifier: 74hc_hct7403_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 19. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 4 7.1 expanded format . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.1 parallel expension . . . . . . . . . . . . . . . . . . . . . . 5 7.1.2 serial expension . . . . . . . . . . . . . . . . . . . . . . . . 5 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 recommended operating conditions. . . . . . . . 6 10 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 11 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 application information. . . . . . . . . . . . . . . . . . 21 13.1 expanded format . . . . . . . . . . . . . . . . . . . . . . 23 13.1.1 sequence 1 (both fifos empty, starting shift-in process) . . . . . . . . . . . . . . . . . . . . . 26 13.1.2 sequence 2 (fifob runs full) . . . . . . . . . . . . . 26 13.1.3 sequence 3 (fifoa runs full) . . . . . . . . . . . . . 27 13.1.4 sequence 4 (both fifos full, starting shift-out) . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.1.5 sequence 5 (fifoa runs empty) . . . . . . . . . . 27 13.1.6 sequence 6 (fifob runs empty) . . . . . . . . . . 27 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 28 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 29 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 30 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 18 contact information. . . . . . . . . . . . . . . . . . . . . 31 19 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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